FIG. 1 is a block diagram of a conventional semiconductor memory device 100. The semiconductor memory device 100 includes a memory cell array 110, a row decoder 120, a precharge circuit 130, a sense amplifier 140, and a controller 150.
The memory cell array 110 includes a plurality of memory cells that are arranged in a matrix of rows and columns. A plurality of wordlines (W/L) define the rows of the matrix, and a plurality of bitlines define the columns of the matrix. A memory cell is located at or adjacent to the intersection of each wordline and bitline. The structure of each memory cell will depend upon the type of semiconductor memory device. For example, each memory cell of a Dynamic Random Access Memory (DRAM) device may include one transistor and one capacitor. In a DRAM memory cell, the gate of the transistor is connected to a wordline of the memory cell array 110, the source of the transistor is connected to a bitline of the memory cell array 110, and the drain of the transistor is connected to the cell capacitor. The amount of charge stored in the capacitor represents one or more bits of data.
The semiconductor memory device 100 of FIG. 1 may operate as follows. When a read command CMD is received, the controller 150 applies a control signal BLPC to the precharge circuit 130. The precharge circuit 130 precharges a bitline in response to the control signal BLPC. After the bitline is precharged, the row decoder 120 activates a wordline of the memory cell array 110 in response to a row address ADDR that is input from a row address buffer (not shown). During a read operation, the data stored in the memory cell is determined based on the difference between the voltage of the bitline that is attached to the memory cell that is being read (i.e., the memory cell at the intersection of the bitline and the activated wordline) and the voltage of a reference bitline. The controller 150 applies a control signal SAE to the sense amplifier 140 that causes the sense amplifier 140 to sense and amplify this voltage difference. Since the capacitance of a bitline is higher than the capacitance of the memory cell, the bitline voltage only fluctuates slightly during a read operation. The bitline voltage sensed and amplified by the sense amplifier 140 is output through an output terminal (not shown). As a result, data stored in any memory cell of the memory cell array 110 may be read out.
As the integration density of a semiconductor memory device increases, the number of memory cells that are connected to each bitline likewise increases. Since memory cells have their own capacitances, the capacitance of a bitline increases as the number of memory cells connected to the bitline increases (the capacitance increases when capacitors are connected in parallel). Due to the increased capacitance, the fluctuation of the bitline voltage during a read operation is reduced. This may make it more difficult to accurately sense data. In addition, the power and time that are required to precharge the bitline increases, and thus system performance may be degraded.